使用UJA1065过程中，需要对寄存器进行各种操作，你是否为配置各种参数，各种模式而计算每个寄存的值，以及寄存器的地址呢？起码我在使用过程中曾经深受其苦，如果对资料不熟悉，或是象我这样对E文不熟使用这款芯片应该不是那么快就能上手吧？这里给出一份NXP的UJA106x官方头文件，我想在编程时应该是一个很不错的帮助吧，这份头文件适用于“UJA1061”，“UJA1065”，“UJA1066”，“UJA1069”。代码如下,希望能过对需要的朋友有所帮助。
/*****************************************************************************/
/* (C) NXP B.V. 2008. */
/* */
/* All rights are reserved. NXP Semiconductors reserves the right to make */
/* changes without notice at any time. NXP Semiconductors makes no warranty, */
/* expressed, implied or statutory, including but not limited to any implied */
/* warranty of merchantibility or fitness for any particular purpose, or */
/* that the use will not infringe any third party patent, copyright or */
/* trademark. NXP Semiconductors must not be liable for any loss or damage */
/* arising from its use. */
/*****************************************************************************/
/* Automotive Innovation Center Hamburg */
/* */
/* FILENAME: UJA106x.h */
/* */
/* VERSION: 1.1 */
/* */
/* DESCRIPTION: Header File for System Basis Chips */
/* UJA1061 / N1E-samples (FT-CAN/LIN SBC) */
/* UJA1065 / N1D-samples (HS-CAN/LIN SBC) */
/* UJA1066 / N1A-samples (HS-CAN SBC) */
/* UJA1069 / N1B-samples (LIN SBC) */
/* */
/* DOCUMENT REF: Data Sheet UJA1061 */
/* Data Sheet UJA1065 */
/* */
/* REVISION HISTORY: */
/* Version Author Date Remarks */
/* 0.9 beta Andr?Ix 17/02/05 Supports UJA1061-N1D; UJA1065-N1C; */
/* UJA1066-N1A; UJA1069-N1A */
/* */
/* 0.91 beta Andr?Ix 16/09/05 Supports UJA1061-N1E; UJA1065-N1D; */
/* UJA1066-N1A; UJA1069-N1B */
/* 1.0 M. Wagner 15/12/05 CAN On-line Listen Mode inserted */
/* 1066 settings corrected */
/* 1.1 J. Habermann 19/08/08 Adapt company name */
/*****************************************************************************/
/*****************************************************************************/
/* Defines */
/*****************************************************************************/
/* Example of how to include this header file in a program: */
/* (e.g. for a UJA1069-N1B SBC derivative) */
/* */
/* #define SBC_TYPE_UJA1069 */
/* #define SBC_VERSION_N1B */
/* */
/* #include “UJA106x.h” */
/*****************************************************************************/
#ifndef UJA106X_H
#define UJA106X_H
#ifdef SBC_TYPE_UJA1061
#ifdef SBC_TYPE_SELECTED
#error “more than one SBC type selected”
#else
#define SBC_TYPE_SELECTED
#endif
#ifdef SBC_VERSION_N1E
#ifdef SBC_VERSION_SELECTED
#error “more than one SBC version selected”
#else
#define SBC_ID 0×0281
#define SBC_VERSION_SELECTED
#endif
#endif
#define SBC_TYPE_CAN_AVAILABLE
#define SBC_TYPE_CAN_LOWSPEED
#define SBC_TYPE_LIN_AVAILABLE
#endif
#ifdef SBC_TYPE_UJA1065
#ifdef SBC_TYPE_SELECTED
#error “more than one SBC type selected”
#else
#define SBC_TYPE_SELECTED
#endif
#ifdef SBC_VERSION_N1D
#ifdef SBC_VERSION_SELECTED
#error “more than one SBC version selected”
#else
#define SBC_ID 0×0205
#define SBC_VERSION_SELECTED
#endif
#endif
#define SBC_TYPE_CAN_AVAILABLE
#define SBC_TYPE_CAN_HIGHSPEED
#define SBC_TYPE_LIN_AVAILABLE
#endif
#ifdef SBC_TYPE_UJA1066
#ifdef SBC_TYPE_SELECTED
#error “more than one SBC type selected”
#else
#define SBC_TYPE_SELECTED
#endif
#ifdef SBC_VERSION_N1A
#define SBC_TYPE_UJA1066_N1A
#ifdef SBC_VERSION_SELECTED
#error “more than one SBC version selected”
#else
#define SBC_ID 0×0086
#define SBC_VERSION_SELECTED
#endif
#endif
#define SBC_TYPE_CAN_AVAILABLE
#define SBC_TYPE_CAN_LOWSPEED
#endif
#ifdef SBC_TYPE_UJA1069
#ifdef SBC_TYPE_SELECTED
#error “more than one SBC type selected”
#else
#define SBC_TYPE_SELECTED
#endif
#ifdef SBC_VERSION_N1B
#ifdef SBC_VERSION_SELECTED
#error “more than one SBC version selected”
#else
#define SBC_ID 0×0109
#define SBC_VERSION_SELECTED
#endif
#endif
#define SBC_TYPE_LIN_AVAILABLE
#endif
// check sbc type and version definition
#ifndef SBC_TYPE_SELECTED
#error “SBC: no SBC type selected”
#else
#ifndef SBC_VERSION_SELECTED
#error “SBC: the selected derivative is not supported”
#endif
#endif
/*****************************************************************************/
/* General definitions */
/*****************************************************************************/
// General Masks
#define SBC_ADDR_MASK 0xC000 // Mask for SBC address
// RO (Read Only)
#define SBC_RO_OFF 0×0000 // Read/Write access
#define SBC_RO_ON 0×1000 // Read only access
/*****************************************************************************/
/* Definitions for Mode Register */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_MOD_REG 0×0000 // Mode Register access
// Mode Register Masks
#define SBC_OM_MASK 0×0038 // Mask for Operating Mode
#define SBC_NWP_MASK 0x0FC0 // Mask for Nominal Watchdog Period
/*—————————————————————————*/
// EN (Enable)
#define SBC_EN_LOW 0×0000 // EN-pin low
#define SBC_EN_HIGH 0×0002 // EN-pin high
// SDM (Software Development Mode)
#define SBC_SDM_OFF 0×0000 // No Software Development Mode
#define SBC_SDM_ON 0×0004 // Software Development Mode active
// OM (Operating Mode)
#define SBC_OM_NOR 0×0008 // Normal Mode Mode
#define SBC_OM_STA 0×0010 // Standby Mode
#define SBC_OM_SLE 0×0020 // Sleep Mode
#define SBC_OM_INI_NOR 0×0028 // Initialising Normal Mode
#define SBC_OM_FLA 0×0038 // Flash Programming Mode
#define SBC_OM_INI_FLA 0×0018 // Initialising Flash Mode
#define SBC_OM_EXI_FLA 0×0030 // Exit Flash Mode
// NWP (Nominal Watchdog Period)
#define SBC_NWP_0 0×0240 // Nominal Watchdog Period 0
#define SBC_NWP_1 0×0300 // Nominal Watchdog Period 1
#define SBC_NWP_2 0×0480 // Nominal Watchdog Period 2
#define SBC_NWP_3 0×0500 // Nominal Watchdog Period 3
#define SBC_NWP_4 0x06C0 // Nominal Watchdog Period 4
#define SBC_NWP_5 0×0900 // Nominal Watchdog Period 5
#define SBC_NWP_6 0x0B40 // Nominal Watchdog Period 6
#define SBC_NWP_7 0x0CC0 // Nominal Watchdog Period 7
#define SBC_NWP_8 0x0D40 // Nominal Watchdog Period 8
#define SBC_NWP_9 0x0D80 // Nominal Watchdog Period 9
/*****************************************************************************/
/* Definitions for System Status Register */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_STA_REG 0×0000 // System Status Register access
// RRS (Read Register Select)
#define SBC_RRS_STA_REG 0×0000 // read System Status Register
// System Status Register Masks
#define SBC_RSS_MASK 0x0F00 // Mask for Reset Source Status
/*—————————————————————————*/
// PWON (Power-On Reset Status)
#define SBC_PWONS_RST 0×0000 // Power on Reset
#define SBC_PWONS_NRST 0×0001 // No Power on Reset
// ENS (Enable Status)
#define SBC_ENS_LOW 0×0000 // EN-pin low
#define SBC_ENS_HIGH 0×0002 // EN-pin high
// SDMS (Software Development Mode Status)
#define SBC_SDMS_OFF 0×0000 // No Software Development Mode
#define SBC_SDMS_ON 0×0004 // Software Development Mode active
// TWS (Temperature Warning Status)
#define SBC_TWS_OK 0×0000 // Temperature below the limit
#define SBC_TWS_ERR 0×0008 // Temperatue exceeds the limit
// LW (Level Wake Status)
#ifdef SBC_TYPE_UJA1066_N1A
#define SBC_LW_LOW 0×0000 // Wake Low Level
#define SBC_LW_HIGH 0×0010 // Wake High Level
#endif
// WLS (Wake Level Status)
#ifndef SBC_TYPE_UJA1066_N1A
#define SBC_WLS_LOW 0×0000 // Wake Low Level
#define SBC_WLS_HIGH 0×0010 // Wake High Level
#endif
// EWS (Edge Wake Status)
#define SBC_EWS_NO_EDG 0×0000 // No level change at WAKE
#define SBC_EWS_EDG 0×0020 // Level change at WAKE
// LWS (LIN Wake Status)
#ifdef SBC_TYPE_LIN_AVAILABLE
#define SBC_LWS_LOW 0×0000 // No Wake event On LIN
#define SBC_LWS_HIGH 0×0040 // Wake event On LIN
#endif
// CWS (CAN Wake Status)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_CWS_LOW 0×0000 // No Wake event On CAN
#define SBC_CWS_HIGH 0×0080 // Wake event On CAN
#endif
// RSS (Reset Source Status)
#define SBC_RSS_POW_ON 0×0000 // Power-on reset
#define SBC_RSS_CYC_WAK 0×0100 // Cyclic wake-up out of sleep
#define SBC_RSS_LOW_V1 0×0200 // Low V1 supply
#define SBC_RSS_INC_V1 0×0300 // V1 current increased
#define SBC_RSS_SHO_V3 0×0400 // V3 shortcut
#define SBC_RSS_FLA_LEF 0×0500 // Flash Mode successfully left
#define SBC_RSS_FLA 0×0600 // SBC ready to enter Flash Mode
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_RSS_CAN 0×0700 // Wake-up via CAN
#endif
#ifdef SBC_TYPE_LIN_AVAILABLE
#define SBC_RSS_LIN 0×0800 // Wake-up via LIN
#endif
#define SBC_RSS_WAK 0×0900 // Wake-up via WAKE
#define SBC_RSS_FAI_SAF 0x0A00 // Wake-up out of Fail Safe
#define SBC_RSS_WD_LAT 0x0B00 // WD triggered too late
#define SBC_RSS_WD_INI 0x0C00 // WD not initialised in time
#define SBC_RSS_WD_EAR 0x0D00 // WD triggered too early
#define SBC_RSS_ILL_MOD 0x0E00 // Illegal Mode Register Code
#define SBC_RSS_INT_LAT 0x0F00 // Interrupt not served in time
/*****************************************************************************/
/* Definitions for System Diagnosis Register */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_DIA_REG 0×0000 // System Diagnosis Register access
// RRS (Read Register Select)
#define SBC_RRS_DIA_REG 0×2000 // read Diagnosis Register
// System Diagnosis Register Masks
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_CANMD_MASK 0×0003 // Mask for CAN Mode Diagnosis
#define SBC_CANFD_MASK 0×0780 // Mask for CAN Failure Diagnosis
#endif
#ifdef SBC_TYPE_LIN_AVAILABLE
#define SBC_LINFD_MASK 0×0060 // Mask for LIN Failure Diagnosis
#endif
/*—————————————————————————*/
// CANMD (CAN Mode Diagnosis)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_CANMD_OFF_LIN 0×0000 // Off-Line Mode or V2 is not active
#define SBC_CANMD_SEL_SLE 0×0001 // Selective Sleep Mode
#define SBC_CANMD_ON_LIN_LIS 0×0001 // On-line Listen mode
#define SBC_CANMD_ON_LIN 0×0002 // On-Line Mode
#define SBC_CANMD_ACT 0×0003 // Active Mode
#endif
// V1D (V1 Diagnosis)
#define SBC_V1D_ERR 0×0000 // V1 too low
#define SBC_V1D_OK 0×0004 // V1 is ok
// V2D (V2 Diagnosis)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_V2D_ERR 0×0000 // V2 disabled due to shortcut
#define SBC_V2D_OK 0×0008 // V2 is ok
#endif
// V3D (V3 Diagnosis)
#define SBC_V3D_ERR 0×0000 // V3 disabled due to shortcut
#define SBC_V3D_OK 0×0010 // V3 is ok
// LINFD (LIN Failure Diagnosis)
#ifdef SBC_TYPE_LIN_AVAILABLE
#define SBC_LINFD_OK 0×0000 // No failure
#define SBC_LINFD_BAT 0×0020 // LIN shorted to VBAT (recessive)
#define SBC_LINFD_GND 0×0040 // LIN shorted to GND (dominant)
#define SBC_LINFD_TXD_DOM 0×0060 // TXD_L clamped dominant
#endif
//CANFD (CAN Failure Diagnosis)
#ifdef SBC_TYPE_CAN_AVAILABLE
#ifdef SBC_TYPE_CAN_LOWSPEED
#define SBC_CANFD_OK 0×0000 // No failure
#define SBC_CANFD_CANH_INT 0×0080 // CANH wire is interrupted
#define SBC_CANFD_CANL_INT 0×0100 // CANL wire is interrupted
#define SBC_CANFD_CANH_BAT 0×0180 // CANH is shorted to VBAT
#define SBC_CANFD_CANH_VCC 0×0200 // CANH is shorted to VCC
#define SBC_CANFD_CANL_GND 0×0280 // CANL is shorted to GND
#define SBC_CANFD_CANH_GND 0×0300 // CANH is shorted to GND
#define SBC_CANFD_CANL_BAT 0×0380 // CANL is shorted to VBAT
#define SBC_CANFD_CANL_VCC 0×0400 // CANL is shorted to VCC
#define SBC_CANFD_CANH_CANL 0×0480 // CANH is shorted to CANL
#define SBC_CANFD_BUS_REC 0×0580 // Bus is clamped recessive
#define SBC_CANFD_BUS_DOM 0×0600 // Bus is clamped dominant
#define SBC_CANFD_RXD_REC 0×0680 // CAN RXD is clamped recessive
#define SBC_CANFD_RXD_DOM 0×0700 // CAN RXD is clamped dominant
#define SBC_CANFD_TXD_DOM 0×0780 // CAN TXD is clamped dominant
#endif
#ifdef SBC_TYPE_CAN_HIGHSPEED
#define SBC_CANFD_CANH_HV 0×0200 // CANH is shorted to VCC or VBAT
#define SBC_CANFD_CANL_GND 0×0280 // CANL is shorted to GND
#define SBC_CANFD_CANH_GND 0×0300 // CANH is shorted to GND
#define SBC_CANFD_CANL_LV 0×0400 // CANL is shorted to VCC or VBAT
#define SBC_CANFD_CANH_CANL 0×0480 // CANL is shorted to CANH
#define SBC_CANFD_BUS_DOM 0×0600 // Bus is clamped dominant
#define SBC_CANFD_RXD_REC 0×0680 // CAN RXD is clamped recessive
#define SBC_CANFD_RXD_DOM 0×0700 // CAN RXD is clamped dominant
#define SBC_CANFD_TXD_DOM 0×0780 // CAN TXD is clamped dominant
#endif
#endif
// GSD (Ground Shift Diagnosis)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_GSD_OK 0×0000 // Ground shift level ok
#define SBC_GSD_ERR 0×0800 // Ground shift level error
#endif
/*****************************************************************************/
/* Definitions for Interrupt Enable Register */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_INT_ENA_REG 0×4000 // Interrupt Enable Register access
// RRS (Read Register Select)
#define SBC_RRS_INT_ENA_REG 0×0000 // read Int. Enable Feedback Register
/*—————————————————————————*/
// LINIE (LIN Interrupt Enable)
#ifdef SBC_TYPE_LIN_AVAILABLE
#define SBC_LINIE_OFF 0×0000 // No LIN interrupt
#define SBC_LINIE_ON 0×0001 // LIN bus wake-up interupt
#endif
// CANIE (CAN Interrupt Enable)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_CANIE_OFF 0×0000 // No CAN interrupt
#define SBC_CANIE_ON 0×0002 // CAN bus wake-up interupt
#endif
// WDRIE (Watchdog Restart Interrupt Enable)
#ifndef SBC_TYPE_UJA1066_N1A
#define SBC_WDRIE_OFF 0×0000 // No watchdog restart
#define SBC_WDRIE_ON 0×0004 // Watchdog restart during watchdog OFF
#endif
// WIE (Wake Interrupt Enable)
#define SBC_WIE_OFF 0×0000 // No WAKE interrupt
#define SBC_WIE_ON 0×0008 // WAKE wake-up interupt
// LINFIE (LIN Failure Interrupt Enable)
#ifdef SBC_TYPE_LIN_AVAILABLE
#define SBC_LINFIE_OFF 0×0000 // No LIN failure interrupt
#define SBC_LINFIE_ON 0×0010 // LIN failure status change interrupt
#endif
// CANFIE (CAN Failure Interrupt Enable)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_CANFIE_OFF 0×0000 // No CAN failure interrupt
#define SBC_CANFIE_ON 0×0020 // CAN failure status change interrupt
#endif
// VFIE (Voltage Failure Interrupt Enable)
#define SBC_VFIE_OFF 0×0000 // No voltage failure interrupt
#define SBC_VFIE_ON 0×0040 // Voltage failure interrupt
// BATFIE (BAT Failure Interrupt Enable)
#define SBC_BATFIE_OFF 0×0000 // No BAT failure interrupt
#define SBC_BATFIE_ON 0×0080 // BAT failure interrupt
// SPIFIE (SPI Failure Interrupt Enable)
#define SBC_SPIFIE_OFF 0×0000 // No SPI failure interrupt
#define SBC_SPIFIE_ON 0×0100 // Wrong number of clock cycles at
// SPI (!=16) interrupt
// GSFIE (Ground Shift Failure Interrupt Enable)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_GSFIE_OFF 0×0000 // No GND shift interrupt
#define SBC_GSFIE_ON 0×0200 // GND shift limit exceeded or dropped
#endif // below interrupt
// OTIE (Over Temperature Interrupt Enable)
#define SBC_OTIE_OFF 0×0000 // No over temperature interrupt
#define SBC_OTIE_ON 0×0400 // Temperature limit exceeded or dropped
// below interrupt
// WTIE (Watchdog Timeout Interrupt Enable)
#define SBC_WTIE_OFF 0×0000 // No interrupt
#define SBC_WTIE_ON 0×0800 // Watchdog overflow occured during
// Standby interrupt
/*****************************************************************************/
/* Definitions for Interrupt Register */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_INT_REG 0×4000 // Interrupt Register access
// RRS (Read Register Select)
#define SBC_RRS_INT_REG 0×2000 // read Interrupt Register
/*—————————————————————————*/
// LINI (LIN Interrupt)
#ifdef SBC_TYPE_LIN_AVAILABLE
#define SBC_LINI 0×0001 // LIN bus wake-up interupt
#endif
// CANI (CAN Interrupt)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_CANI 0×0002 // CAN bus wake-up interupt
#endif
// WDRI (Watchdog Restart Interrupt)
#ifndef SBC_TYPE_UJA1066_N1A
#define SBC_WDRI 0×0004 // Watchdog restart interrupt
#endif
// WI (Wake Interrupt)
#define SBC_WI 0×0008 // Edge at WAKE detected
// LINFI (LIN Failure Interrupt)
#ifdef SBC_TYPE_LIN_AVAILABLE
#define SBC_LINFI 0×0010 // LIN failure status change
#endif
// CANFI (CAN Failure Interrupt)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_CANFI 0×0020 // CAN failure status change
#endif
// VFI (Voltage Failure Interrupt)
#define SBC_VFI 0×0040 // Short at voltage Vx detected
// BATFI (BAT Failure Interrupt)
#define SBC_BATFI 0×0080 // Falling edge at SENSE detected
// SPIFI (SPI Failure Interrupt)
#define SBC_SPIFI 0×0100 // Wrong number of clock cycles at
// SPI (!=16)
// GSI (Ground Shift Interrupt)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_GSI 0×0200 // GND shift limit passed
#endif
// OTI (Over Temperature Interrupt)
#define SBC_OTI 0×0400 // Temperature limit passed
// WTI (Watchdog Timeout Interrupt)
#define SBC_WTI 0×0800 // Watchdog overflow occured during
// Standby
/*****************************************************************************/
/* Definitions for System Configuration Register */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_CON_REG 0×8000 // System Configuration Register access
// RRS (Read Register Select)
#define SBC_RRS_CON_REG 0×0000 // read System Config. Feedback Register
// System Configuration Register Masks
#define SBC_V3C_MASK 0x00C0 // Mask for V3 Configuration
/*—————————————————————————*/
// IC (INH Control)
#ifdef SBC_TYPE_UJA1066_N1A
#define SBC_IC_OFF 0×0000 // INH Mode -> INH = “float”
#define SBC_IC_ON 0×0001 // INH Mode -> INH = “HIGH”
#endif
#ifndef SBC_TYPE_UJA1066_N1A
// ILC (INH/LIMP Control)
#define SBC_ILC_LOW 0×0000 // INH / LIMP Control -> Low (Limp Home)
#define SBC_ILC_HIG 0×0001 // INH / LIMP Control -> High (Inhibit)
// ILEN (INH/LIMP Enable)
#define SBC_ILEN_OFF 0×0000 // INH / LIMP disabled
#define SBC_ILEN_ON 0×0002 // INH / LIMP enabled
#endif
// WSC (WAKE Sample Control)
#define SBC_WSC_CON 0×0000 // WAKE Mode -> Continously sample
#define SBC_WSC_CYC 0×0004 // WAKE Mode -> Cyclic sample
// WEN (WAKE Enable)
#define SBC_WEN_OFF 0×0000 // Wake-up via Wake PIN Disabled
#define SBC_WEN_ON 0×0008 // Wake-up via Wake PIN Enabled
// V1CMC (V1 Current Monitor Control) // Behaviour at watchdog off:
#define SBC_V1CMC_WD 0×0000 // V1 current activates watchdog
#define SBC_V1CMC_RES 0×0010 // V1 current activates reset
// V1RTHC (V1 Reset Threshold Control)
#ifdef SBC_TYPE_UJA1066_N1A
#define SBC_V1RTHC_NOR 0×0000 // Normal V1 under-volt. thresh.
#define SBC_V1RTHC_LOW 0×0020 // Low V1 under-volt. thresh.
#endif
// V3C (V3 Control)
#define SBC_V3C_OFF 0×0000 // V3 off
#define SBC_V3C_ON 0×0040 // V3 on
#define SBC_V3C_CYC_16MS 0×0080 // V3 Cyclic Mode (16ms period)
#define SBC_V3C_CYC_32MS 0x00C0 // V3 Cyclic Mode (32ms period)
// RLC (Reset Length Control)
#define SBC_RLC_1MS 0×0000 // Reset length is 1ms
#define SBC_RLC_20MS 0×0100 // Reset length is 20 ms
// GSTH (Ground Shift Threshold Control)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_GSTHC_LOW 0×0000 // 0.75V absolute ground shift threshold
#define SBC_GSTHC_HIG 0×0200 // 1.5V absolute ground shift threshold
#endif
/*****************************************************************************/
/* Definitions for Physical Layer Control Register */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_PHY_REG 0xC000 // Physical Layer Control
// Register access
// RRS (Read Register Select)
#define SBC_RRS_PHY_REG 0×0000 // read Physical Layer Control
// Feedback Register
/*—————————————————————————*/
#ifdef SBC_TYPE_LIN_AVAILABLE
// LTC (LIN Transmitter Control)
#define SBC_LTC_ON 0×0000 // LIN transmitter is enabled
#define SBC_LTC_OFF 0×0001 // LIN transmitter is disabled
// LWEN (LIN Wake-up Enable)
#define SBC_LWEN_OFF 0×0000 // LIN Wake-up Disabled
#define SBC_LWEN_ON 0×0002 // LIN Wake-up Enabled
// LDC (LIN Driver Control)
#define SBC_LDC_NOR 0×0000 // LIN driver conform LIN 2.0 standard
#define SBC_LDC_ENH 0×0004 // Enhanced LIN driver capability
// LSC (LIN Slope Control)
#define SBC_LSC_20K 0×0000 // 20.0 kbit/s
#define SBC_LSC_10K 0×0008 // 10.0 kbit/s
// LMC (LIN Mode Control)
#define SBC_LMC_OFF 0×0000 // LIN Off-line Mode
#define SBC_LMC_ACT 0×0010 // LIN Active Mode
#endif
#ifdef SBC_TYPE_CAN_AVAILABLE
// CSC (CAN Split Control)
#ifdef SBC_TYPE_CAN_HIGHSPEED
#define SBC_CSC_ON 0×0000 // Split term. On
#define SBC_CSC_OFF 0×0020 // Split term. Off
#endif
// CMC (CAN Mode Control)
#define SBC_CMC_AUT 0×0000 // CAN Auto Mode
#define SBC_CMC_ACT 0×0040 // CAN Active Mode
// CRC (CAN Receiver Control)
#define SBC_CRC_NOR 0×0000 // No internal feedback (normal)
#define SBC_CRC_TEST 0×0080 // TXD_C forwarded to RXD_C (test)
// CTC (CAN Transmitter Control)
#define SBC_CTC_ON 0×0000 // CAN transmitter is enabled
#define SBC_CTC_OFF 0×0100 // CAN transmitter is disabled
// COTC (CAN Offline Time Control)
#define SBC_COTC_64MS 0×0000 // 64ms Off-Line time
#define SBC_COTC_256MS 0×0200 // 256ms Off-Line time
// CPNC (CAN Partial Networking Control)
#define SBC_CPNC_OFF 0×0000 // CAN Partial Networking off
#define SBC_CPNC_ON 0×0400 // CAN Partial Networking on
// V2C (V2 Control)
#ifndef SBC_TYPE_UJA1066_N1A
#define SBC_V2C_OFF 0×0000 // V2 is off in Off-Line Mode
#define SBC_V2C_ON 0×0800 // V2 active in Off-Line Mode
#endif
#endif
/*****************************************************************************/
/* Definitions for Special Mode Register */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_SPE_REG 0×4000 // Special Mode Register access
/*—————————————————————————*/
// V1RTHC (V1 Reset Threshold Control)
#ifndef SBC_TYPE_UJA1066_N1A
#define SBC_V1RTHC_0_9 0×0000 // 0.9 x V1 under-volt. thresh.
#define SBC_V1RTHC_0_8 0×0008 // 0.8 x V1 under-volt. thresh.
#define SBC_V1RTHC_0_7 0×0010 // 0.7 x V1 under-volt. thresh.
#endif
// WDPRE (Watchdog Prescaler)
#define SBC_WDPRE_1 0×0000 // Scalefactor = 1
#define SBC_WDPRE_15 0×0020 // Scalefactor = 1.5
#define SBC_WDPRE_25 0×0040 // Scalefactor = 2.5
#define SBC_WDPRE_35 0×0060 // Scalefactor = 3.5
// ERREM (Error-pin Emulation Mode)
#ifdef SBC_TYPE_CAN_AVAILABLE
#define SBC_ERREM_OFF 0×0000 // EN-pin behaves with EN functionality
#define SBC_ERREM_ON 0×0100 // EN-pin signals CAN failures active LOW
#endif
// ISDM (Init Software Development Mode)
#define SBC_ISDM_OFF 0×0000 // Normal Watchdog & Interrupt
#define SBC_ISDM_ON 0×0200 // No WD Reset, no interrupt monitoring
/*****************************************************************************/
/* Definitions for General Purpose Register 0 */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_GP0_REG 0×8000 // General Purpose Register 0 access
// RRS (Read Register Select)
#define SBC_RRS_GP0_REG 0×2000 // read General Purpose 0 Feedback
// Register
/*****************************************************************************/
/* Definitions for General Purpose Register 1 */
/*****************************************************************************/
// ADDR (Address)
#define SBC_ADDR_GP1_REG 0xC000 // General Purpose Register 1 access
// RRS (Read Register Select)
#define SBC_RRS_GP1_REG 0×2000 // read General Purpose 1 Feedback
// Register
/*****************************************************************************/
#endif // UJA106X_H
